---
title: "amd-ross-agentic-ai-assistant"
description: "Agent Skills for Developing Products with AMD Embedded Technologies"
canonical: https://agentpluginsdirectory.com/plugins/amd-ross-agentic-ai-assistant
last-updated: 2026-10-06
---

# amd-ross-agentic-ai-assistant
Agent Skills for Developing Products with AMD Embedded Technologies
- Slug: amd-ross-agentic-ai-assistant
- Publisher: Advanced Micro Devices, Inc.
- Repository: https://github.com/Xilinx/ross-ai-assistant
- Manifest: plugin.json
- Version: 2026.9.1
- License: MIT
- Category (editorial): other
- Skills: 49 (hls-architect, hls-array-to-stream, hls-burst-inference, hls-component-basic-info, hls-cosim-report, hls-dataflow-infos, hls-dataflow, hls-flattenable, hls-ii-diagnose, hls-impl-report, hls-line-buffer, hls-matlab-to-cpp, hls-optimize, hls-perf-pragma, hls-pipe-decomp, hls-pipeline, hls-pragma-scope, hls-run-flow, hls-stencil-pattern, hls-synth-report, hls-synthesizable, hw-ila-debug, hw-vio-debug, segcfg-aie, segcfg-design-check, segcfg-design-considerations, segcfg-dfx, segcfg-hw-manager, segcfg-overview, segcfg-pl-reload, vai-aie-compiler-oriented-optimizations, vai-aie-kernel-development, vai-custom-op-candidates, vai-custom-op-implementation, vai-custom-op, vai-dequantize-model, vai-fe-args, vai-ffn-quantization, vai-flag-configuration, vai-partition-analysis, vai-peak-bandwidth-analysis, vai-perf-analysis, vai-quantization-guide, vivado-ip-configurator, vivado-revision-control, vivado-rtl-elaboration-analysis, vivado-rtl-lint, vivado-simulate-rtl, vivado-timing-methodology-checks)
- MCP servers: 0
- Stars: 88
- Repository created: 2026-08-21
- Repository last pushed: 2026-09-30
- Publisher type: Organization
- Listing: https://agentpluginsdirectory.com/plugins/amd-ross-agentic-ai-assistant
- Schema: https://agent-plugins.org/schemas/1.0.0/plugin.schema.json

## What amd-ross-agentic-ai-assistant does, in the publisher's words

Agent skills for AMD FPGA/SoC development.

New here? Start with the Getting Started guide. See docs for FAQ, MCP reference, and support.

From the project README, punctuation lightly normalized. Full text: https://raw.githubusercontent.com/Xilinx/ross-ai-assistant/HEAD/README.md

## Skills

- hls-architect: Convert input code to a multi-stage HLS dataflow, validate with the other hls skills, then hand off to optimize.
- hls-array-to-stream: Analyze whether a given C/C++ code snippet follows the recommended coding style for array-to-stream conversion in Vitis HLS. Keywords: array, stream, HLS, pragma, ap_fifo, axis, interface
- hls-burst-inference: Analyze whether burst inference optimization can be applied to a given C/C++ code snippet in Vitis HLS. Keywords: burst, HLS, pragma, m_axi, AXI, memory, optimization
- hls-component-basic-info: Get Vitis HLS component basic informations for a given HLS component. The basic informations includes component name, source files, testbench files, include paths and top function
- hls-cosim-report: Get Vitis HLS cosimulation report information for a given HLS component.
- hls-dataflow-infos: Get Vitis HLS dataflow process/channel informations for a given HLS component.
- hls-dataflow: Analyze whether a given C/C++ code snippet contains a canonical dataflow region for Vitis HLS. Keywords: dataflow, HLS, pragma, canonical, stream, PIPO, hls:task
- hls-flattenable: Analyze whether a given C/C++ code snippet contains a flattenable loop nest for Vitis HLS.
- hls-ii-diagnose: Diagnose the root cause of an II (initiation interval) violation in a synthesized Vitis HLS component, classify the bottleneck, and cite the supporting evidence, without modifying source or running flows.
- hls-impl-report: Get Vitis HLS implementation report information (post-route clock, resource utilization,Fail Fast table gives utilization percentages) for a given HLS component.
- hls-line-buffer: Fill the HLS line-buffer and window-buffer gap for stencil kernels, including TOTAL_ITER drain and verification. Use when generated buffer code misses the drain or the check.
- hls-matlab-to-cpp: Convert MATLAB sample-based code to plain C++ frame-based loops, analyze algorithm, generate C++ that compiles with g++, verify against MATLAB golden, then hand off to /hls-architect for HLS dataflow architecture.
- hls-optimize
- hls-perf-pragma
- hls-pipe-decomp
- hls-pipeline
- hls-pragma-scope
- hls-run-flow
- hls-stencil-pattern
- hls-synth-report
- hls-synthesizable
- hw-ila-debug
- hw-vio-debug
- segcfg-aie
- segcfg-design-check
- segcfg-design-considerations
- segcfg-dfx
- segcfg-hw-manager
- segcfg-overview
- segcfg-pl-reload
- vai-aie-compiler-oriented-optimizations
- vai-aie-kernel-development
- vai-custom-op-candidates
- vai-custom-op-implementation
- vai-custom-op
- vai-dequantize-model
- vai-fe-args
- vai-ffn-quantization
- vai-flag-configuration
- vai-partition-analysis
- vai-peak-bandwidth-analysis
- vai-perf-analysis
- vai-quantization-guide
- vivado-ip-configurator
- vivado-revision-control
- vivado-rtl-elaboration-analysis
- vivado-rtl-lint
- vivado-simulate-rtl
- vivado-timing-methodology-checks

Descriptions come from the frontmatter of each SKILL.md, punctuation lightly normalized.