---
title: "hdl-rtl"
description: "ASIC HDL skills: Verilog/SystemVerilog format, synthesizable DUT constraints, TESTBED/PATTERN generation, flow environment setup, preflight check before VCS/DC, and opt-in RTL timing local rewrites."
canonical: https://agentpluginsdirectory.com/plugins/hdl-rtl
last-updated: 2026-10-06
---

# hdl-rtl
ASIC HDL skills: Verilog/SystemVerilog format, synthesizable DUT constraints, TESTBED/PATTERN generation, flow environment setup, preflight check before VCS/DC, and opt-in RTL timing local rewrites.
- Slug: hdl-rtl
- Publisher: Marco
- Repository: https://github.com/akira2963753/ic-design-skill
- Manifest: plugin.json
- Version: 0.1.0
- License: MIT
- Category (editorial): other
- Skills: 6 (asic-check, asic-env, design-format, dv-format, rtl-constraint, rtl-opt)
- MCP servers: 0
- Stars: 0
- Repository created: 2026-08-22
- Repository last pushed: 2026-09-03
- Publisher type: User
- Listing: https://agentpluginsdirectory.com/plugins/hdl-rtl
- Schema: https://agent-plugins.org/schemas/1.0.0/plugin.schema.json

## What hdl-rtl does, in the publisher's words

An ASIC HDL plugin for Cursor, Claude Code, and Codex. It watches formatting when you write Verilog / SystemVerilog, and whether the DUT is synthesizable. Testbench skeletons and sim / syn / gate flow files are separate commands. It will not rewrite timing unless you ask.

normal is not in this plugin. Stimulus, scoreboard, and actually running VCS / DC are still on you.

A project usually looks like this:

From the project README, punctuation lightly normalized. Full text: https://raw.githubusercontent.com/akira2963753/ic-design-skill/HEAD/README.md

## Skills

- asic-check: Final preflight check before VCS simulation or DC synthesis. Reports RTL syntax, makefile, run scripts, file.f, and path errors. Does not verify functional logic. Use when the user calls /asic-check, asks to check the environment, or wants a last check before sim or syn. Do not apply while generati…
- asic-env: Builds ASIC project flow files for 00_TESTBED / 01_RTL / 02_SYN / 03_GATE: file.f, makefile, 01_run, 02_run, 03_run. Asks 90nm vs 16nm for StdCell. Use when the user calls /asic-env, asks to set up the environment, generate file.f, makefile, or run scripts. Do not apply when only writing RTL or tes…
- design-format: Constrains Verilog/SystemVerilog format quality for generated or edited.v/.sv files. Enforces 4-space indent, no alignment padding, compact if(/for(/case(, always_ff/always_comb, localparam vs define.vh, ternary (x)? a: b, centered section headers, and a four-field file banner. Use when generatin…
- dv-format: Generates TESTBED.sv and PATTERN.sv for SystemVerilog verification. TESTBED owns FSDB dump and gate-level SDF annotation; PATTERN owns sim-based stimulus, drive_reset, checks, and in-file SVA. Applies design-format to all generated files. Use when the user calls /dv-format, asks to generate a testb…
- rtl-constraint: Enforces synthesizable SystemVerilog RTL constraints for DUT code. Requires full assignment in always_comb to avoid latches, synthesizable-only constructs, a single driver per signal, constant loop bounds, no combinational loops, reset via if(!rst_n) not declaration inits, and top modules that are…
- rtl-opt: Applies local RTL timing optimizations in the user's SystemVerilog style (CSE, hierarchical shared conditions, decode, bit-slice, balanced trees, late mux, equivalent arith rewrite). Use only when the user explicitly asks to optimize RTL, timing, critical path, slack, PPA, or names rtl-opt / /rtl-o…

Descriptions come from the frontmatter of each SKILL.md, punctuation lightly normalized.