---
title: "hdl-rtl"
description: "ASIC HDL skills: Verilog/SystemVerilog format, synthesizable DUT constraints, TESTBED/PATTERN generation, flow environment setup, preflight check before VCS/DC, and opt-in RTL timing local rewrites."
canonical: https://agentpluginsdirectory.com/plugins/hdl-rtl
last-updated: 2026-08-23
---

# hdl-rtl
ASIC HDL skills: Verilog/SystemVerilog format, synthesizable DUT constraints, TESTBED/PATTERN generation, flow environment setup, preflight check before VCS/DC, and opt-in RTL timing local rewrites.
- Slug: hdl-rtl
- Publisher: Marco
- Repository: https://github.com/akira2963753/ic-design-skill
- Manifest: plugin.json
- Version: 0.1.0
- License: MIT
- Category (editorial): other
- Skills: 6 (asic-check, asic-env, design-format, dv-format, rtl-constraint, rtl-opt)
- MCP servers: 0
- Stars: 0
- Listing: https://agentpluginsdirectory.com/plugins/hdl-rtl
- Schema: https://agent-plugins.org/schemas/1.0.0/plugin.schema.json