--- title: "openada" description: "Open agent-EDA contracts, deterministic drivers, and tool-independent engineering skills." canonical: https://agentpluginsdirectory.com/plugins/openada last-updated: 2026-09-21 --- # openada Open agent-EDA contracts, deterministic drivers, and tool-independent engineering skills. - Slug: openada - Publisher: Simra Tech - Repository: https://github.com/simra-tech/OpenADA - Manifest: plugin.json - Version: 0.4.0 - License: MIT - Category (editorial): other - Skills: 11 (analyze-feedback-stability, analyze-spectral-linearity, assess-asic-timing, assess-pvt-and-yield, assess-synthesis-and-inference, bootstrap-asic-project, characterize-analog-block, close-layout-incrementally, openada, review-circuit-simulation, review-rtl-architecture) - MCP servers: 0 - Stars: 26 - Repository created: 2026-07-13 - Repository last pushed: 2026-08-12 - Publisher type: Organization - Listing: https://agentpluginsdirectory.com/plugins/openada - Schema: https://agent-plugins.org/schemas/1.0.0/plugin.schema.json ## What openada does, in the publisher's words The open interface between agents and EDA. Versioned engineering intent in. Auditable engineering evidence out. OpenADA is building the open semantic boundary between design agents and deterministic EDA tools. An agent states an engineering intent, netlist a schematic, run a simulation, check DRC, compare LVS, and a driver translates it into the native tool's CLI, API, files, environment, and run policy. OpenADA returns compact evidence for the agent's next decision while the native design files and EDA artifacts remain authoritative. - execution.status: completed means the native process ran. - engineering.status: pass means the operation's fixed assertion passed. - A successful simulation establishes valid analysis evidence; it does not by itself establish that the circuit meets its specification. - DRC clean and LVS match do not establish circuit performance or foundry signoff. From the project README, punctuation lightly normalized. Full text: https://raw.githubusercontent.com/simra-tech/OpenADA/HEAD/README.md ## Skills - analyze-feedback-stability: Analyze feedback-loop stability with backend-independent OpenADA evidence. Use for differential, common-mode, nested, feed-forward, regulator, or switched-loop questions involving operating-point validity, loop injection and probe identity, gain and phase crossover review, phase or gain margin, clo… - analyze-spectral-linearity: Analyze waveform spectra and linearity with backend-independent OpenADA evidence. Use for FFT setup, coherent sampling, windowing, alias folding, SFDR, harmonic distortion, HD2 or HD3, sampled-data spurs, before/after linearity comparisons, or diagnosing an untrustworthy spectral scalar while prese… - assess-asic-timing: Assess synthesis-stage ASIC setup and hold timing with backend-independent OpenADA evidence. Use when validating a mapped netlist against a Liberty corner and SDC, reviewing WNS, TNS, unconstrained endpoints and worst setup/hold path summaries, diagnosing whether a timing miss is trustworthy, compa… - assess-pvt-and-yield: Plan and assess deterministic PVT, sweep, mismatch, and Monte Carlo campaigns through composable OpenADA intents. Use when expanding explicit corner matrices, checking specifications across process-voltage-temperature or load conditions, accounting for pass/fail/unknown points, computing bounded ra… - assess-synthesis-and-inference: Assess ASIC synthesis, technology mapping, and inferred hardware with backend-independent OpenADA evidence. Use when reviewing whether RTL produced a complete Liberty-mapped netlist, investigating unexpected register, latch, memory, arithmetic, or mux structures, comparing controlled synthesis expe… - bootstrap-asic-project: Bootstrap and coordinate a fresh open-source ASIC project when the PDK, EDA runtime, project configuration, or physical-design collateral is missing or ambiguous. Use for requests to choose an open PDK, provision compatible tools, create a reproducible ASIC workspace, turn RTL such as a CPU into a… - characterize-analog-block: Analyze, plan, and review backend-independent analog-block behavior and characterization through OpenADA semantic intents. Use for qualitative schematic or topology reasoning, transient-phase and scaling analysis, device-sizing tradeoffs, defining a characterization matrix for an amplifier, regulat… - close-layout-incrementally: Close analog, mixed-signal, custom-digital, or top-level IC layout through small visually reviewed increments with fresh DRC, LVS, extraction, and performance evidence. Use when editing or debugging GDS, OASIS, Magic, KLayout, or custom-cell layout; placing matched or parasitic-critical devices; ro… - openada: Discover, invoke, and interpret open-source EDA tools through OpenADA's versioned CLI contract. Use for semiconductor or electronics work involving Xschem schematics (.sch), SPICE simulation, GDS/KLayout DRC, Netgen LVS, Verilog/SystemVerilog lint, Yosys ASIC synthesis, OpenSTA timing, PDK discover… - review-circuit-simulation: Review circuit-simulation evidence and recommend the next engineering action through OpenADA's backend-independent circuit.simulate contract. Use when assessing a SPICE operating-point, DC, AC, or transient run; deciding whether simulation evidence is trustworthy; comparing normalized evidence acro… - review-rtl-architecture: Review ASIC RTL architecture with backend-independent OpenADA lint and structural evidence. Use for SystemVerilog or Verilog design reviews involving hierarchy, clocks and resets, state/control structure, parameterization, inferred latches or combinational loops, arithmetic width, signedness, overf… Descriptions come from the frontmatter of each SKILL.md, punctuation lightly normalized.